A) Field
The embodiments discussed herein are directed to a semiconductor device, which may relate to a semiconductor device having pads for connection to an external circuit and for inspection.
B) Description of the Related Art
It is well known that as moisture permeates into a circuit region of a semiconductor integrated circuit device, the performance of the semiconductor integrated circuit device is degraded. An interlayer insulating film of the semiconductor integrated circuit device is often made of silicon oxide. Silicon oxide has a high affinity with moisture. In order to prevent permeation of moisture and hydrogen, a cover film having a moisture blocking function is formed on a multilayer wiring and a moisture blocking ring is formed along a peripheral edge of a semiconductor chip.
JP-A-2002-270608 (applicant: Fujitsu VLSI Ltd) proposes that in a semiconductor device having a damascene wiring structure burying a wiring pattern and via conductors in an interlayer insulating film, a moisture blocking ring extending along a peripheral edge of a chip is made of lamination of via rings formed in the same layers as those of the via conductors and wiring rings formed in the same layers as those of the wiring patterns.
JP-A-2005-175204 (applicant: Fujitsu Ltd) proposes that a first moisture blocking ring is disposed inside the pads and a second moisture blocking ring is disposed outside the pads. If a conductive moisture blocking ring is used, the first moisture blocking ring should be cut around wirings connected to the pads.
The development of ferro-electric memory (Fe RAM) is in progress which uses a ferro-electric capacitor and stores information by utilizing reversible polarization of ferro-electric material. A ferro-electric memory is a nonvolatile memory whose stored information will not be erased even if power supply is shut down, and is expected to realize high integration, high speed driving, high durability and low power consumption.
A ferro-electric memory stores information by utilizing hysteresis characteristics of ferro-electric material. A ferro-electric capacitor having a ferro-electric film as a capacitor dielectric film sandwiched between a pair of electrodes generates polarization corresponding to a voltage applied across the electrodes, and retains the polarization even after the applied voltage is removed. As the polarity of the applied voltage is reversed, the polarity of polarization is also reversed. By detecting this polarization, information can be read. As the material of the ferro-electric film, ferro-electric oxide material having a perovskite crystal structure is used mainly, such as PZT(Pb(Zr1-xTix)O3) and SBT(SrBi2Ta2O9) having a large polarization quantity, e.g., about 10 μC/cm2 to 30 μC/cm2. In order to form a ferro-electric oxide film having excellent characteristics, the film is required to be formed or to be subjected to heat treatment in an oxidizing atmosphere , and a lower electrode (also an upper electrode when necessary) is often made of noble metal hard to be oxidized, noble metal maintaining conductivity even if it is oxidized, or noble metal oxide.
As moisture permeates from external, moisture can reach wirings, capacitors, transistors and the like through the interlayer insulating film. As moisture reaches a capacitor particularly a ferro-electric capacitor, the characteristics of a dielectric film particularly a ferro-electric film are deteriorated. If the ferro-electric film is reduced by hydrogen derived from permeated moisture and oxygen defects are formed, crystallinity of the dielectric film becomes bad. The characteristics are deteriorated such as a reduced residual polarization quantity and a lowered dielectric constant. Similar phenomena occur by long term use. As hydrogen permeates, deterioration of the characteristics becomes more direct than moisture.
A semiconductor integrated circuit device has pads in the layer same as the uppermost wiring layer or above the uppermost wiring layer. Probe needles are abutted on the pads for inspection, or wires are bonded to the pads for connection to an external circuit. The pad has a relatively large size as compared to other wiring patterns, and the upper surface is exposed on which a probe needle is abutted or to which a connection wire for an external circuit is bonded. Until a semiconductor integrated circuit device is completed, a plurality of inspections are performed, and only the products judged good at a final stage is packaged. Pads for inspection and for external connection are required to be in an exposed state.
As a probe needle is abutted on a pad during inspection, the pad may have a crack. Scribe pad layout is known wherein bonding pads are disposed in a chip region, and inspection pads are disposed in a scribe region outside the chip region. Since inspection pads are cut off by a scribe process after inspections, the bonding pads will not have a crack. However, if the inspection pads are disposed in the scribe region together with alignment marks and test element group (TEG), the moisture blocking ring is required to be cut away around the wirings for interconnecting scribe pads with the chip circuit. It is desired not to use scribe pads because the moisture blocking ability will be lowered. According to another countermeasure, inspection pads and bonding pads are separately disposed in the chip region, and after inspections, the inspection pads are covered with a protection film. With this countermeasure, however, the number of pads in the chip region increases, hindering high integration.
There are strong demands for using a ferro-electric memory in a tag, a card and the like. For this application, a ferro-electric memory device is desired to be made much smaller.